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DSD
2010
IEEE

Low Power FPGA Implementations of 256-bit Luffa Hash Function

11 years 5 days ago
Low Power FPGA Implementations of 256-bit Luffa Hash Function
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Two major gate level techniques are introduced in order to reduce the power consumption, namely the pipeline technique (with some variants) and the use of embedded RAM blocks instead of general purpose logic elements.
Paris Kitsos, Nicolas Sklavos, Athanassios N. Skod
Added 06 Dec 2010
Updated 06 Dec 2010
Type Conference
Year 2010
Where DSD
Authors Paris Kitsos, Nicolas Sklavos, Athanassios N. Skodras
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