Sciweavers

Share
GLVLSI
2000
IEEE

Low power high speed analog-to-digital converter for wireless communications

9 years 26 days ago
Low power high speed analog-to-digital converter for wireless communications
A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy reduction. The low power dissipation is a vital factor when we consider the chip reliability and integrity. The low energy consumption is a critical factor when we deal with battery operated devices like PCSs. This technique may also be used to extend the attainable flash converter resolution by pre-calculating the most significant bits.
A. E. Hussein, Mohamed I. Elmasry
Added 31 Jul 2010
Updated 31 Jul 2010
Type Conference
Year 2000
Where GLVLSI
Authors A. E. Hussein, Mohamed I. Elmasry
Comments (0)
books