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ASPDAC
2001
ACM

Low power implementation of a turbo-decoder on programmable architectures

9 years 3 months ago
Low power implementation of a turbo-decoder on programmable architectures
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal architectures. Thus low power implementations of advanced channel decoding techniques are mandatory. In this paper we present a low power implementation of the most sophisticated channel decoding algorithm (Turbo-decoding) on programmable architectures. Low power optimization is performed on two abstraction levels: on system level by the use of an intelligent cancellation technique, on implementation level by the use of dynamic voltage scaling. With these techniques we can reduce the worst case energy consumption to 55% using data of state-of-the-art processors. Our approach is also applicable for hardware implementations. To the best of our knowledge, this is the first in-depth study of low power implementations of Turbo-decoders based on voltage scheduling for third generation wireless systems.
Frank Gilbert, Alexander Worm, Norbert Wehn
Added 23 Aug 2010
Updated 23 Aug 2010
Type Conference
Year 2001
Where ASPDAC
Authors Frank Gilbert, Alexander Worm, Norbert Wehn
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