Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

11

DAC
2005
ACM

favoriteEmaildiscussreport

109views Computer Architecture» more DAC 2005»

Low power network processor design using clock gating

14 years 5 months ago

Low power network processor design using clock gating

Download nepsim.cs.ucr.edu

Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate multiprocessing and multithreading to achieve maximum parallel processing capabilities. We observed that under low incoming traffic rates, most processing elements (PEs) in NPs are nearly idle and yet still consume dynamic power. This paper develops a low power technique to reduce the activities of PEs according to the varying traffic volume. We propose to monitor the average number of idle threads in a time window, and gate off the clock network of unused PEs when a subset of PEs is enough to handle the network traffic. To accommodate different applications and network parameters (i.e. packet size, arrival rate), the thresholds of turning on/off PEs will be dynamically tuned on-the-fly. We show that our technique brings significant reduction in power consumption (up to 30%) of NPs with no packet loss and littl...

Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo

Real-time Traffic

DAC 2005 | Design Automation | Low Incoming Traffic | NPs Incorporate Multiprocessing | Unused Pes |

claim paper

Related Content

» A low power VLIW processor generation method by means of extracting nonredundant activatio...

» Low power sequential circuit design by using priority encoding and clock gating

» Challenges in clockgating for a low power ASIC methodology

» Power and thermal effects of SRAM vs LatchMux design styles and clock gating choices

» Low power synthesis of dynamic logic circuits using finegrained clock gating

» TopDown Design of a LowPower MultiChannel 25GbitsChannel Gated Oscillator ClockRecovery Ci...

» Deterministic Clock Gating for Microprocessor Power Reduction

» Reducing Power Consumption of an Embedded DSP Platform through the ClockGating Technique

» A multiple clocking scheme for low power RTL design

Post Info
More Details (n/a)

Added	13 Nov 2009
Updated	13 Nov 2009
Type	Conference
Year	2005
Where	DAC
Authors	Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo

Comments (0)