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ASPDAC
2001
ACM

Low power techniques for address encoding and memory allocation

13 years 7 months ago
Low power techniques for address encoding and memory allocation
- This paper presents encoding techniques to optimize the switching activity on a multiplexed DRAM address bus. The DRAM switching activity can be classified either as external (between two consecutive addresses) or internal (between the row and column addresses of the same address). To eliminate the external switching activity for sequential access, we propose an optimal encoding, Pyramid code, for conventional DRAM mode as well as Burst Pyramid code for burst mode DRAM. To minimize the internal switching activity, we propose Scattered Paging for both random and sequential access patterns by exploiting the built-in virtual memory mechanism, which is commonly present on modern processors.
Wei-Chung Cheng, Massoud Pedram
Added 23 Aug 2010
Updated 23 Aug 2010
Type Conference
Year 2001
Where ASPDAC
Authors Wei-Chung Cheng, Massoud Pedram
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