Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

10

ISLPED
2003
ACM

favoriteEmaildiscussreport

111views Hardware» more ISLPED 2003»

A low-power VLSI architecture for turbo decoding

13 years 9 months ago

A low-power VLSI architecture for turbo decoding

Download www.ifp.illinois.edu

Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of blockinterleaved computation followed by folding, retiming and voltage scaling. Block-interleaved Computation can be applied to any data processing unit that operates on data

Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer

Real-time Traffic

Data Processing Unit | ISLPED 2003 | Low-power Architecture | Turbo Decodings |

claim paper

Related Content

» Low power architecture of the softoutput Viterbi algorithm

» VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond

» VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax

» On the Implementation of a LowPower IEEE 80211a Compliant Viterbi Decoder

» Architectural strategies for lowpower VLSI turbo decoders

» A Low PowerDelay Product PageBased Address Bus Coding Method

» CouplingDriven Signal Encoding Scheme for LowPower Interface Design

» High Speed MaxLogMAP Turbo SISO Decoder Implementation Using Branch Metric Normalization

Post Info
More Details (n/a)

Added	05 Jul 2010
Updated	05 Jul 2010
Type	Conference
Year	2003
Where	ISLPED
Authors	Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer

Comments (0)