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2002
IEEE

Maintaining Packet Order In Two-stage Switches

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Maintaining Packet Order In Two-stage Switches
-- High performance packet switches frequently use a centralized scheduler (also known as an arbiter) to determine the configuration of a non-blocking crossbar. The scheduler often limits the scalability of the system because of the frequency and complexity of its decisions. A recent paper by C.-S. Chang et al. introduces an interesting two-stage switch, in which each stage uses a trivial deterministic sequence of configurations. The switch is simple to implement at high speed and has been proved to provide 100% throughput for a broad class of traffic. Furthermore, there is a bound between the average delay of the two-stage switch and that of an ideal output-queued switch. However, in its simplest form, the switch mis-sequences packets by an arbitrary amount. In this paper, building on the two-stage switch, we present an algorithm called Full Frames First (FFF), that prevents mis-sequencing while maintaining the performance benefits (in terms of throughput and delay) of the basic two-s...
Isaac Keslassy, Nick McKeown
Added 15 Jul 2010
Updated 15 Jul 2010
Type Conference
Year 2002
Where INFOCOM
Authors Isaac Keslassy, Nick McKeown
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