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GLVLSI
2010
IEEE

Methodology to achieve higher tolerance to delay variations in synchronous circuits

8 years 11 months ago
Methodology to achieve higher tolerance to delay variations in synchronous circuits
A methodology is proposed for designing robust circuits exhibiting higher tolerance to process and environmental variations. This higher tolerance is achieved by exploiting the interdependence between the setup and hold times, reducing the delay uncertainty caused by variations. An algorithm is proposed to determine the interdependent setup-hold pair of a register. A data path designed with the proposed setup-hold pair improves the overall tolerance to variations. The methodology is evaluated for several technologies to determine the overall reduction in delay uncertainty. Categories and Subject Descriptors B.7.m [Integrated Circuits]: General Terms Algorithms, design
Emre Salman, Eby G. Friedman
Added 10 Jul 2010
Updated 10 Jul 2010
Type Conference
Year 2010
Where GLVLSI
Authors Emre Salman, Eby G. Friedman
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