A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms

A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementing many embedded systems. Paradoxically, the integration that makes modern FPGAs an attractive computing substrate also makes the development of energy efficient FPGA designs very challenging in practice. This is due to the many alternatives available for implementing a desired functionality and a lack of high-level models of FPGA architectures that can accurately capture the energy dissipation behavior of alternatives. To address these issues, we propose a methodology for energy efficient FPGA designs using malleable algorithms. Malleable algorithms are used to expose the architecture-platform aware specifications of alternate implementations of the desired functionalities. Our methodology consists of three major design steps: domain-specific energy performance modeling, development of malleable algorithms, a...

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Jingzhao Ou, Viktor K. Prasanna
• Keywords: Designs, Energy Efficient Fpga, FPL 2004, Hardware, Malleable Algorithms