Methods for true power minimization

9 years 4 months ago
Methods for true power minimization
This paper presents methods for efficient power minimization at circuit and micro-architectural levels. The potential energy savings are strongly related to the energy profile of a circuit. These savings are obtained by using gate sizing, supply voltage, and threshold voltage optimization, to minimize energy consumption subject to a delay constraint. The true power minimization is achieved when the energy reduction potentials of all tuning variables are balanced. We derive the sensitivity of energy to delay for each of the tuning variables connecting its energy saving potential to the physical properties of the circuit. This helps to develop understanding of optimization performance and identify the most efficient techniques for energy reduction. The optimizations are applied to some examples that span typical circuit topologies including inverter chains, SRAM decoders, and adders. At a delay of 20% larger than the minimum, energy savings of 40% to 70% are possible, indicating that ac...
Robert W. Brodersen, Mark Horowitz, Dejan Markovic
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2002
Authors Robert W. Brodersen, Mark Horowitz, Dejan Markovic, Borivoje Nikolic, Vladimir Stojanovic
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