Microarchitecture-aware floorplanning using a statistical design of experiments approach

Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi-cycle delays. Although such a wire pipelining strategy allows higher operating frequencies, it can reduce the delivered performance of a microarchitecture, since the extra flip-flops inserted may increase the operation latencies and stall cycles. Moreover, the addition of latencies on some wires can have a large impact on the overall performance while other wires are relatively insensitive to additional latencies. This varying sensitivity suggests the need for a throughput-aware strategy for pipelining the interconnects that interacts closely with the physical design step, which determines the lengths of these multicycle wires. We use a statistical design of experiments strategy based on a multifactorial design, which intelligently uses a limited number of simulations to rank the importance of the wires. Whe...

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar
• Keywords: Additional Latencies, DAC 2005, Design Automation, Operation Latencies, Wire Pipelining Strategy