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DAC
1994
ACM

Minimal Delay Interconnect Design Using Alphabetic Trees

9 years 3 months ago
Minimal Delay Interconnect Design Using Alphabetic Trees
Abstract - We propose a new algorithm for the performancedriven interconnect design problem, based on alphabetic trees. The interconnect topology is determined in a global manner and does not greedily add edges as in conventional approaches. The algorithm can handle cases where the sink capacitances are different. Good results are obtained while running two to sixty times faster than three existing algorithms on practical instances.
Ashok Vittal, Malgorzata Marek-Sadowska
Added 09 Aug 2010
Updated 09 Aug 2010
Type Conference
Year 1994
Where DAC
Authors Ashok Vittal, Malgorzata Marek-Sadowska
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