The Minimax Cache: An Energy-Efficient Framework for Media Processors

This work is based on our philosophy of providing interlayer system-level power awareness in computing systems [26, 27]. Here, we couple this approach with our vision of multipartitioned memory systems [18, 19, 25], where memory accesses are separated based on their static predictability and memory footprint and managed with various compiler controlled techniques. We show that media applications are mapped more efficiently when scalar memory accesses are redirected to a minicache. Our results indicate that a partitioned 8K cache with the scalars being mapped to a 512 byte minicache can be more efficient than a 16K monolithic cache from both performance and energy point of view for most applications. In extensive experiments, we report 30% to 60% energy-delay product savings over a range of system configurations and different cache sizes.

• Type: Conference
• Year: 2002
• Where: HPCA
• Authors: Osman S. Unsal, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
• Keywords: Computer Architecture, HPCA 2002, Interlayer System-level Power, Multipartitioned Memory Systems, Scalar Memory Accesses