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2003
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Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization

9 years 7 months ago
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous assignment of Vth with gate sizing. We propose an efficient algorithm based on linear programming that jointly performs Vth assignment and gate sizing to minimize total power under delay constraints. First, linear programming assigns the optimal amounts of slack to gates based on power-delay sensitivity. Then, an optimal gate configuration, in terms of Vth and transistor sizes, is selected by an exhaustive local search. Benchmark results for the algorithm show 32% reduction in power consumption on average, compared to sizing only power minimization. There is up to a 57% reduction for some circuits. The flow can be extended to dual supply voltage libraries to yield further power savings. Categories and Subject Descriptors B.6.3 [Design Aids] General Terms Algorithms, Performance, Design Keywords Dual Threshold,...
David Nguyen, Abhijit Davare, Michael Orshansky, D
Added 05 Jul 2010
Updated 05 Jul 2010
Type Conference
Year 2003
Where ISLPED
Authors David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer
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