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DATE
2009
IEEE

Minimization of NBTI performance degradation using internal node control

9 years 6 months ago
Minimization of NBTI performance degradation using internal node control
—Negative Bias Temperature Instability (NBTI) is a significant reliability concern for nanoscale CMOS circuits. Its effects on circuit timing can be especially pronounced for circuits with standby-mode equipped functional units because these units can be subjected to static NBTI stress for extended periods of time. This paper proposes internal node control, in which the inputs to individual gates are directly manipulated to prevent this static NBTI fatigue. We give a mixed integer linear program formulation for an optimal solution to this problem. The optimal placement of internal node control yields an average 26.7% reduction in NBTI-induced delay over a ten year period for the ISCAS85 benchmarks. We find that the problem is NP-complete and present a linear-time heuristic that can be used to quickly find near-optimal solutions. The heuristic solutions are, on average, within 0.17% of optimal and all were within 0.60% of optimal.
David R. Bild, Gregory E. Bok, Robert P. Dick
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors David R. Bild, Gregory E. Bok, Robert P. Dick
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