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2008
IEEE

Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures

10 years 2 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the router in a NoC [10]) used to implement logical channels multiplexed across the physical channel in a router output port for QoS supported on-chip communication. In the first step, the number of virtual channels is minimized during the mapping of tasks to the NoC at the design time of a System on Chip (SoC) for which we use a swarm intelligence-based Ant Colony Optimization (ACO) algorithm. In the second step, a probabilistic approach based on the traffic model of the application is used to further minimize the number of virtual channels. We achieve on average 90.2% reduction in the number of virtual channels compared to a fixed stateof-the-art (i.e. QNoC [1]) allocation for the E3S embedded application benchmark suit. The reduction depends on the designer and the QoS parameter, and it is dependent on the speci...
Mohammad Abdullah Al Faruque, Jörg Henkel
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where DATE
Authors Mohammad Abdullah Al Faruque, Jörg Henkel
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