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MICRO
1992
IEEE

MISC: a Multiple Instruction Stream Computer

9 years 3 months ago
MISC: a Multiple Instruction Stream Computer
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC architecture uses multiple asynchronous processing elements to separate a program into streams that can be executed in parallel, and integrates a conflict-free message passing system into the lowest level of the processor design to facilitate low latency intra-MISC communication. This approach allows for increased machine parallelism with minimal code expansion, and provides an alternative approach to single instruction stream multi-issue machines such as SuperScalar and VLIW. - 1
Gary S. Tyson, Matthew K. Farrens, Andrew R. Plesz
Added 10 Aug 2010
Updated 10 Aug 2010
Type Conference
Year 1992
Where MICRO
Authors Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun
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