Miss reduction in embedded processors through dynamic, power-friendly cache design

Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result, traditional methods for addressing performance and determinism become inadequate. This paper explores a new data cache design for use in modern high-performance embedded processors that will dynamically improve execution time, power efficiency, and determinism within the system. The simulation results show significant improvement in cache miss ratios and reduction in power consumption of approximately 30% and 15%, respectively. Categories and Subject Descriptors B.3.2 [Memory Structures]: Design Styles--cache memories; C.3 [Computer Systems Organization]: SpecialPurpose and Application-Based Systems--real-time and embedded systems General Terms Design, Performance Keywords embedded processors, data cache, multi-core, dynamic associativity

• Type: Conference
• Year: 2008
• Where: DAC
• Authors: Garo Bournoutian, Alex Orailoglu
• Keywords: Cache Miss Ratios, DAC 2008, Data Cache Design, Design Automation, Keywords Embedded Processors