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DAC
1999
ACM

Model Order-Reduction of RC(L) Interconnect Including Variational Analysis

9 years 8 months ago
Model Order-Reduction of RC(L) Interconnect Including Variational Analysis
As interconnect feature sizes continue to scale to smaller dimensions, long interconnect can dominate the IC timing performance, but the interconnect parameter variations make it difficult to predict these dominant delay extremes. This paper presents a model order-reduction technique for RLC interconnect circuits that includes variational analysis to capture manufacturing variations. Matrix perturbation theory is combined with dominant-pole-analysis and Krylov-subspace-analysis methods to produce reduced-order models with direct inclusion of statistically independent manufacturing variations. The accuracy of the resulting variational reduced-order models is demonstrated on several industrial examples.
Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
Added 02 Aug 2010
Updated 02 Aug 2010
Type Conference
Year 1999
Where DAC
Authors Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas
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