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DAC
2006
ACM

Modeling and minimization of PMOS NBTI effect for robust nanometer design

9 years 6 months ago
Modeling and minimization of PMOS NBTI effect for robust nanometer design
Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the degradation of NBTI in both static and dynamic operations. Model scalability and generality are comprehensively verified with experimental data over a wide range of process and bias conditions. By implementing the new model into SPICE for an industrial 90nm technology, key insights are obtained for the development of robust design solutions: (1) the most effective techniques to mitigate the NBTI degradation are VDD tuning, PMOS sizing, and reducing the duty cycle; (2) an optimal VDD exists to minimize the degradation of circuit performance; (3) tuning gate length or the switching frequency has little impact on the NBTI effect; (4) a new switching scenario is identified for worst case timing analysis during NBTI stress. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids– performance ana...
Rakesh Vattikonda, Wenping Wang, Yu Cao
Added 13 Jun 2010
Updated 13 Jun 2010
Type Conference
Year 2006
Where DAC
Authors Rakesh Vattikonda, Wenping Wang, Yu Cao
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