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IESS
2009
Springer

Modeling Cache Effects at the Transaction Level

8 years 6 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast simulation speed for use in design space exploration. Previous efforts have enabled designers to estimate performance with Transaction Level Modeling (TLM) of software processors but this technique typically does not account for the effect of memory latencies. Modeling latency effects of a cache can greatly increase accuracy of the simulation and assist designers in choosing appropriate algorithms. In this article, we show the implementation of a cache model and its integration into a processor TLM. We demonstrate a method for extracting information about memory accesses from the final binary and ing them into cache model accesses. Our methodology is tested on a common embedded processor application with two algorithms exhibiting different cache behaviors. Our experiments show that the cache model can achieve...
Ardavan Pedram, David Craven, Andreas Gerstlauer
Added 19 Feb 2011
Updated 19 Feb 2011
Type Journal
Year 2009
Where IESS
Authors Ardavan Pedram, David Craven, Andreas Gerstlauer
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