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2003
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Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic

9 years 7 months ago
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectures, the choice of an efficient architecture and reconfiguration scheme for a given application is a complex task. Tools for exploration of lternatives at higher abstraction levels are needed. This paper describes the modeling and simulation of a dynamically reconfigurable hardware implementation of the Fast Fourier Transform – FFT using rewriting-logic. It is shown that rewriting-logic can be used as a framework for fast design space exploration, providing a quick evaluation of different reconfigurable solutions.
Mauricio Ayala-Rincón, Rodrigo B. Nogueira,
Added 05 Jul 2010
Updated 05 Jul 2010
Type Conference
Year 2003
Where SBCCI
Authors Mauricio Ayala-Rincón, Rodrigo B. Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein
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