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EURODAC
1994
IEEE

Modeling shared variables in VHDL

13 years 7 months ago
Modeling shared variables in VHDL
A set of concurrent processes communicating through shared variables is an often used model for hardware systems. This paper presents three modeling techniques for representing such shared variables in VHDL, depending on the acceptable constraints on accesses to the variables. Also a set of guidelines for handling atomic updates of multiple shared variables is given.
Jan Madsen, Jens P. Brage
Added 08 Aug 2010
Updated 08 Aug 2010
Type Conference
Year 1994
Where EURODAC
Authors Jan Madsen, Jens P. Brage
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