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2006

Modelling and simulation of off-chip communication architectures for high-speed packet processors

8 years 4 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications architectures for line cards. The simulator uses the state-of-the-art software design techniques to provide the user with a flexible, robust and comprehensive tool that can evaluate k-ary n-cube based network topologies under non-uniform traffic patterns. The simulator provides full control over essential network parameters and flow control mechanisms such as virtual channels and sub-channeling. We compare three low-dimensional k-ary n-cube based interconnects that can fit into the physical limitations on line cards, where each one of these interconnects has multiple processor-memory configurations. Performance results show that k-ary n-cube architectures perform better than existing interconnects, and they can sustain current line rates and higher. In addition, we provide performance tradeoffs between multiple...
Jacob Engel, Daniel Lacks, Taskin Koçak
Added 13 Dec 2010
Updated 13 Dec 2010
Type Journal
Year 2006
Where JSS
Authors Jacob Engel, Daniel Lacks, Taskin Koçak
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