Modelling hardware verification concerns specified in the e language: an experience report

13 years 11 months ago

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e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In recent years, the continued growth of the testbenches developed at Infineon Technologies has resulted in their becoming difficult to understand, maintain and extend. Consequently, a decision was document the testbenches at a higher level of abstraction. Accordingly, we attempted to model our legacy test suites with an existing aspect-oriented modelling approach. In this paper we describe our experience of applying Theme/UML, an aspectoriented modelling approach, to the representation of aspectoriented testbenches implemented in e. It emerged that the common aspect-oriented concepts supported by Theme/UML were not sufficient to adequately represent the e language, primarily due to e’s dynamic, temporal nature. Based on this experience we propose a number of requirements that must be addressed before aspect-orie...

Darren Galpin, Cormac Driver, Siobhán Clark

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