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Models for Embedded Application Mapping onto NoCs: Timing Analysis

9 years 3 months ago
Models for Embedded Application Mapping onto NoCs: Timing Analysis
Networks-on-chip (NoCs) are an emergent communication infrastructure, which can be designed to deal with growing system complexity and technology evolution. The efficient use of NoCs needs techniques for application cores mapping, allowing reducing the message latency and consequently the overall execution time. To obtain mappings that fulfill the requirements during highlevel design, appropriate models for NoCs and application come mandatory. High abstraction levels modeling may lead to unreliable estimates. On the other hand, detailed models may imply complex algorithms and high computational effort, with unacceptable computation time to get satisfactory results. NoC modeling for latency estimation requires capturing some infrastructure characteristics like topology and routing policies. Application cores models have to capture the application behavior, in terms of computation and/or communication. For instance, communication weighted models (CWM) and communication dependence model ...
César A. M. Marcon, Márcio Eduardo K
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where RSP
Authors César A. M. Marcon, Márcio Eduardo Kreutz, Altamiro Amadeu Susin, Ney Laert Vilar Calazans
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