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EUROPAR
2004
Springer

Modular On-chip Multiprocessor for Routing Applications

9 years 5 months ago
Modular On-chip Multiprocessor for Routing Applications
Abstract. Simulation platforms for network processing still have difficulties in finding a good compromise between speed and accuracy. This makes it difficult to identify the causes of performance bottlenecks: Are they caused by application, hardware architecture, or by a specificity of the operating system? We propose a simulation methodology for a multiprocessor network processing platform which contains sufficient detail to permit very precise simulation and performance evaluation while staying within reasonable limits of both specification and simulation time. As a case study, we show how a model can be developed for a IPv4 packet routing application, exhibiting the performance and scalability bottlenecks and can thus be used to reason about architectural alternatives.
Saifeddine Berrayana, Etienne Faure, Daniela Geniu
Added 01 Jul 2010
Updated 01 Jul 2010
Type Conference
Year 2004
Where EUROPAR
Authors Saifeddine Berrayana, Etienne Faure, Daniela Genius, Frédéric Pétrot
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