Modular Exponent Realization on FPGAs

The article describes modular exponent calculations used widely in cryptographic key exchange protocols. The measures for hardware consumption and execution speed based on argument bit width and algorithm rank are created. The partitioning of calculations is analyzed with respect to interconnect signal numbers and added delay. The partitioned blocks are used for implementation approximations of two different multiplier architectures. Examples are provided for 3 families of FPGAs: XC4000, XC6200 and FLEX10k

• Type: Conference
• Year: 1998
• Where: FPL
• Authors: Juri Põldre, Kalle Tammemäe, Marek Mandre
• Keywords: Argument Bit Width, Cryptographic Key Exchange, FPL 1998, Hardware, Modular Exponent Calculations