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DATE
2009
IEEE

A monitor interconnect and support subsystem for multicore processors

9 years 6 months ago
A monitor interconnect and support subsystem for multicore processors
Abstract— In many current SoCs, the architectural interface to onchip monitors is ad hoc and inefficient. In this paper, a new architectural approach which advocates the use of a separate lowoverhead subsystem for monitors is described. A key aspect of this approach is an on-chip interconnect specifically designed for monitor data with different priority levels. The efficiency of our monitor interconnect is assessed for a multicore system using both an interconnect and a system-level simulator. Collected monitor information is used by a dedicated processor to control the frequency and voltage of individual multicore processors. Experimental results show that the new low-overhead subsystem facilitates employment of thermal and delay-aware dynamic voltage and frequency scaling.
Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burl
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burleson, Russell Tessier
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