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ISQED
2005
IEEE

A More Effective CEFF

9 years 8 months ago
A More Effective CEFF
Precise chip-level timing requires careful modeling of the interaction between logic drivers and interconnect. Existing static-timing analysis methodologies generate models for drivers with lumped capacitive loads. This necessitates the translation of the actual loading and interconnect parasitics into a single effective capacitance [12]. Existing approaches to perform that translation are either iterative in nature or involve iterative procedure to solve nonclosed form equations and thus costly in CPU time. This paper presents a new accurate and simple closed form approach to deal with effective capacitance.
Sani R. Nassif, Zhuo Li
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where ISQED
Authors Sani R. Nassif, Zhuo Li
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