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2007
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MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture

10 years 2 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP) to applications by means of a sparsely interconnected array of functional units and register files. As high-ILP architectures achieve only low parallelism when executing partially sequential code segments, which is also known as Amdahl's law, this paper proposes to extend ADRES to MT-ADRES (Multi-Threaded ADRES) to also exploit thread-level parallelism. On MT-ADRES architectures, the array can be partitioned in multiple smaller arrays that can execute threads in parallel. Because the partition can be changed dynamically, this extension provides more flexibility than a multi-core approach. This article presents details of the enhanced architecture and results obtained from an MPEG-2 decoder implementation that exploits a mix of thread-level parallelism and instruction-level parallelism.
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be
Added 12 Aug 2010
Updated 12 Aug 2010
Type Conference
Year 2007
Where ARC
Authors Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic
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