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2008
IEEE

A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator

8 years 8 months ago
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also hardware resource intensive and require longer latencies than fixed point operators to complete. Due to the reduced logic density of FPGAs relative to ASICs, it is often only possible to accelerate a portion of a floating point application in hardware. This paper presents an application-specific architecture for the hardware acceleration of a complete Fourier Integral Operator (FIO) kernel used in seismic imaging on a multi-FPGA platform. The design utilizes several floating point computing elements (CEs) to calculate the FIO kernel in parallel stages on multiple FPGAs. A detailed study of floating point CEs, including a Fast Fourier Transform (FFT) CE, and a complete FIO prototype implementation on the BEE2 platform is described. The prototype implementation has a 12.4x increase in throughput over an optimize...
Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where ASAP
Authors Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary F. Margrave
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