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ISMVL
2008
IEEE

Multiple Valued Logic Using 3-State Quantum Dot Gate FETs

8 years 8 months ago
Multiple Valued Logic Using 3-State Quantum Dot Gate FETs
Abstract—This paper presents fundamental logic structures designed using novel quantum dot gate FETs with three-state characteristics. This three-state FET manifests itself as a transistor with a stable ”intermediate” state, where the drain current remains constant over a range of input gate voltages due to a change in the threshold voltage over this range. We have developed a simplified circuit model that accounts for this intermediate state. Using this model, we have designed rudimentary logic circuits for use in multiple-valued logic circuits.
John A. Chandy, Faquir C. Jain
Added 31 May 2010
Updated 31 May 2010
Type Conference
Year 2008
Where ISMVL
Authors John A. Chandy, Faquir C. Jain
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