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2006
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A Multithreaded Soft Processor for SoPC Area Reduction

9 years 7 months ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling systems with large numbers of intellectual property (IP) blocks. Soft processors control IP blocks, which are accessed by the processor either as peripheral devices or/and by using custom instructions (CIs). In large systems, chip multiprocessors (CMPs) are used to execute many programs concurrently. When these programs require the use of the same IP blocks which are accessed as peripheral devices, they may have to stall waiting for their turn. In the case of CIs, the FPGA logic blocks that implement the CIs may have to be replicated for each processor. In both of these cases FPGA area is wasted, either by idle soft processors or the replication of CI logic blocks. This paper presents a multithreaded (MT) soft processor for area reduction in SoPC implementations. An MT processor allows multiple programs to acces...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where FCCM
Authors Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown
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