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ESTIMEDIA
2007
Springer

Network Calculus Applied to Verification of Memory Access Performance in SoCs

10 years 1 months ago
Network Calculus Applied to Verification of Memory Access Performance in SoCs
SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes the performance of a SoC under design hard to predict. Network calculus defines the concept of flow and has been successfully used to analyse the performance of communication networks. We propose to apply network calculus to the verification of memory access latencies. Two novel network elements, packet stretcher and packet compressor, are used to model the SoC interconnect and DRAM controller. We further extend the flow concept with a degree and make use of the peak characteristics of a flow to tighten the bounds in the analysis. We present a video playback case study and show that the proposed application of network calculus allows us to statically verify that all requirements on memory access latency are fulfilled.
Tomas Henriksson, Pieter van der Wolf, Axel Jantsc
Added 07 Jun 2010
Updated 07 Jun 2010
Type Conference
Year 2007
Where ESTIMEDIA
Authors Tomas Henriksson, Pieter van der Wolf, Axel Jantsch, Alistair C. Bruce
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