Network-on-Chip: The Intelligence is in The Wire

10 years 6 months ago
Network-on-Chip: The Intelligence is in The Wire
In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at 90nm technology and below. Although much progress has been made in connecting the various components encompassed in communication networks for System-on-Chip (SoC) designs (e.g. processor-specific bus architectures, interface adapters, etc.), until now there has not been the possibility to consider a chip-wide architectural methodology that takes into account all typical NoC design requirements. As design complexity continues to increase, a more global approach is required to effectively transport and manage both onchip and off-chip communication traffic, optimize wire efficiency and permit designs to scale in size, complexity, and IP block usage. The system described in this work is based on an innovative switching fabric that allows designers to build an efficient and scalable architecture for NoC implement...
Gérard Mas, Philippe Martin
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2004
Where ICCD
Authors Gérard Mas, Philippe Martin
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