A Networked FPGA-Based Hardware Implementation of a Neural Network Application

This paper describes a networked FPGA-based implementation of the FAST (Flexible Adaptable-Size Topology) architecture, a Arti cial Neural Network (ANN) that dynamically adapts its size. Most ANN models base their ability to adapt to problems on changing the strength of the interconnections between computational elements according to a given learning algorithm. However, constrained interconnection structures may limit such ability. Field programmable hardware devices are very well adapted for the implementation of ANN with in-circuit structure adaptation. To realize this implementation we used a network of Labomat 3 boards (a recon gurable platform developed in our laboratory), which communicate with each other using TCP/IP or a faster, direct hardware connection.

• Type: Conference
• Year: 2000
• Where: FCCM
• Authors: Héctor Fabio Restrepo, Ralph Hoffmann, Andrés Pérez-Uribe, Christof Teuscher, Eduardo Sanchez
• Keywords: Cial Neural Network, FCCM 2000, Most ANN Models, Networked Fpga-based Implementation, VLSI