A New Combinational Logic Minimization Technique with Applications to Cryptology

Abstract. A new technique for combinational logic optimization is described. The technique is a two-step process. In the first step, the nonlinearity of a circuit – as measured by the number of non-linear gates it contains – is reduced. The second step reduces the number of gates in the linear components of the already reduced circuit. The technique can be applied to arbitrary combinational logic problems, and often yields improvements even after optimization by standard methods has been performed. In this paper we show the results of our technique when applied to the S-box of the Advanced Encryption Standard (AES [5]). This is an experimental proof of concept, as opposed to a full-fledged circuit optimization effort. Nevertheless the result is, as far as we know, the circuit with the smallest gate count yet constructed for this function. We have also used the technique to improve the performance (in software) of several candidates to the Cryptographic Hash Algorithm Competition...

• Type: Conference
• Year: 2010
• Where: WEA
• Authors: Joan Boyar, René Peralta
• Keywords: Algorithms, Arbitrary Combinational Logic, Combinational Logic, Combinational Logic Optimization, WEA 2010