Sciweavers

Share
DAC
2006
ACM

A new hybrid FPGA with nanoscale clusters and CMOS routing

10 years 27 days ago
A new hybrid FPGA with nanoscale clusters and CMOS routing
In this paper we propose a hybrid FPGA using nanoscale clusters with an architecture similar to clusters of traditional CMOS FPGAs. The proposed cluster is made of a crossbar of nanowires configured to implement the required LUTs and intra-cluster MUXes. A CMOS interface is also proposed to provide configuration and latching for the nanoscale cluster. Inter-cluster routing is assumed to remain at CMOS scale. Experimental analysis is performed to evaluate area and performance of the hybrid FPGA and results are compared with traditional fully CMOS FPGA (scaled to 22nm). Up to 75% area reduction was obtained from implementing MCNC benchmarks on hybrid FPGA. Performance of the hybrid FPGA is shown to be close to that of CMOS FPGA. Categories & Subject Descriptors: B.7.1 [INTEGRATED CIRCUITST]: Types and Design Styles-Advanced technologies, B.8.2 [PERFORMANCE AND RELIABILITY]: Performance Analysis and Design Aids General Terms: Design, Performance
Reza M. Rad, Mohammad Tehranipoor
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2006
Where DAC
Authors Reza M. Rad, Mohammad Tehranipoor
Comments (0)
books