A New Method for Testing Re-Programmable PLAs

: We present a method for obtaining a minimal set of test configurations and their associated set oftest patterns that completely tests re-programmable Programmable Logic Arrays (PLAs) including EEPROM, UV-EPROM, and SRAM based re-programmable PLAs typically found in Complex Programmable Logic Devices (CPLDs). The resultant set of test configurations and vectors detect all single and multiple stuck -at faults (including line and transistor faults) as well as all brid ging faults in the PLA. Previously proposed test methods proposed for EEPROM based PLAs [1,2] require additional test hardware as well as a large number of test configurations and vectors for complete testing. Our approach requires no modification to the PLA and only two or four test configurations, depending on the ratio of PLA product terms to inputs.

• Type: Journal
• Year: 2000
• Where: ET
• Authors: Charles E. Stroud, James R. Bailey, Johan R. Emmert
• Keywords: ET 2000, Programmable Logic, Re-programmable Programmable Logic, Test Configurations