NOC architecture design for multi-cluster chips

For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconnections must be flexible and scalable in order to provide parallel on-demand computing. For this reason, the goal of this paper is to present design decisions of a MultiCluster NoC (MCNoC) architecture in order to support collective communication patterns through topology reconfiguration on an FPGA-based multi-cluster chip. The MCNoC's results show a small area occupation, low power consumption and high performance.

• Type: Conference
• Year: 2008
• Where: FPL
• Authors: Henrique C. Freitas, Philippe Olivier Alexandre Navaux, Tatiana Gadelha Serra dos Santos
• Keywords: FPGA-based Multi-cluster Chip, FPL 2008, Hardware, Onchip Interconnection Networks, Parallel On-demand Computing