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GLVLSI
1998
IEEE

Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning

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Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning
In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally update the weights from the analog back-propagation signals for fast onchip learning. In this circuit, the weight is stored as a 5-bit digital number, which controls the gates of five pass transistors allowing five binary-weighted (1,2,4,8,16) voltage references to integrate at a voltage adder. The output of the voltage adder is the analog weight. The 5-bit register is designed as an up/down counter so that every pulse on the up/down input will increase/decrease the weight by one level out of 32 possible levels. The learning circuit takes the analog graded error signal and generates two pulse streams for up/down counting depending on the sign of the error signal. The duration of the pulse stream is proportional to the magnitude of the error signal. This complete modular synaptic body (storage and learning tech...
Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A.
Added 04 Aug 2010
Updated 04 Aug 2010
Type Conference
Year 1998
Where GLVLSI
Authors Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. Ayoubi
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