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10

ICES
2003
Springer

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A Note on Designing Logical Circuits Using SAT

13 years 9 months ago

A Note on Designing Logical Circuits Using SAT

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Abstract. We present a systematic procedure for the synthesis and minimisation of digital circuits using propositional satisﬁability. We encode the truth table into a canonical sum of at most k diﬀerent minterms, which is then passed to one randomised search procedure that minimises k. The solution for a minimal k is the satisﬁable representation of the resulting circuit. We show how to use an interesting feature of the local search landscape in this minimisation. This approach can be very useful because we can generate exact minimal solutions within reasonably computational resources.

Giovani Gomez Estrada

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Exact Minimal Solutions | ICES 2003 | Local Search Landscape | Systematic Procedure |

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Added	06 Jul 2010
Updated	06 Jul 2010
Type	Conference
Year	2003
Where	ICES
Authors	Giovani Gomez Estrada

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