A novel 32-bit scalable multiplier architecture

In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable to higher-order multiplication. This multiplier topology is highly conducive for an electronic design automation (EDA) tool based implementation. A 32-bit version of this multiplier has been implemented using a standard ASIC design methodology and one variation of the standard design methodology in a 0.25µm technology. This 32-bit multiplier has a latency of 3.56ns. Categories and Subject Descriptors B.7.1 [Microprocessors and microcomputers]: General Terms Multiplier,Design, Performance Keywords Multiplier, Architecture,CMOS VLSI

• Type: Conference
• Year: 2003
• Where: GLVLSI
• Authors: Yeshwant Kolla, Yong-Bin Kim, John Carter
• Keywords: 32-bit Multiplier, GLVLSI 2003, Hybrid Multiplier Architecture, Multiplier Topology, VLSI