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2005
IEEE

Novel architecture for loop acceleration: a case study

9 years 11 months ago
Novel architecture for loop acceleration: a case study
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this architecture. To illustrate the advantages of this approach, we investigate a JPEG encoding algorithm and accelerate one of its loop by implementing it in a coprocessor. We contrast the acceleration by implementing the critical segment as two different coprocessors and a set of customized instructions. The two different coprocessor approaches are: a high-level synthesis (HLS) approach; and a custom coprocessor approach. The HLS approach provides a faster method of generating coprocessors. We show that a loop performance improvement of 2.57x is achieved using the custom coprocessor ap
Seng Lin Shee, Sri Parameswaran, Newton Cheung
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where CODES
Authors Seng Lin Shee, Sri Parameswaran, Newton Cheung
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