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ISVLSI
2003
IEEE

Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS

9 years 7 months ago
Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS
SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly increasing gate tunneling current caused by an ultra-thin gate oxide, even at scaled VDDs [8]. This paper analyzes these effects in detail and proposes a number of novel circuit styles to minimize them. Simulation results are based on model parameters from an AMD 0.25 µm PD-SOI process.
Koushik K. Das, Richard B. Brown
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ISVLSI
Authors Koushik K. Das, Richard B. Brown
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