Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

9

VLSID
2002
IEEE

favoriteEmaildiscussreport

95views VLSI» more VLSID 2002»

A Novel Method to Improve the Test Efficiency of VLSI Tests

14 years 4 months ago

A Novel Method to Improve the Test Efficiency of VLSI Tests

Download www.cs.york.ac.uk

This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal of minimizing the test cost. Best and worst case bounds are established for the performance of a reordered sequence compared to the original sequence of test application. SEMATECH test data and simulation results are used throughout to illustrate the ideas.

Hailong Cui, Sharad C. Seth, Shashank K. Mehta

Real-time Traffic

Computer Architecture | SEMATECH Test Data | Test Application | Test Cost | VLSID 2002 |

claim paper

Related Content

» First Level Hold A Novel LowOverhead Delay Fault Testing Technique

» A novel approach for Kbest MIMO detection and its VLSI implementation

» Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods

» An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers

» Improving the Test of NoCBased SoCs with Help of Compression Schemes

» Efficient Techniques for Directed Test Generation Using Incremental Satisfiability

» Reordering Algorithm for Minimizing Test Power in VLSI Circuits

» A Novel Lowoverhead Delay Testing Technique for Arbitrary TwoPattern Test Application

» A Novel Functional Test Generation Method for Processors Using Commercial ATPG

Post Info
More Details (n/a)

Added	01 Dec 2009
Updated	01 Dec 2009
Type	Conference
Year	2002
Where	VLSID
Authors	Hailong Cui, Sharad C. Seth, Shashank K. Mehta

Comments (0)