A Novel VLSI Architecture of Fixed-complexity Sphere Decoder

10 years 3 months ago
A Novel VLSI Architecture of Fixed-complexity Sphere Decoder
Fixed-complexity sphere decoder (FSD) is a recently proposed technique for multiple-input multiple-output (MIMO) detection. It has several outstanding features such as constant throughput and large potential parallelism, which makes it suitable for efficient VLSI implementation. However, to our best knowledge, no VLSI implementation of FSD has been reported in the literature, although some FPGA prototypes of FSD with pipeline architecture have been developed. These solutions achieve very high throughput but at very high cost of hardware resources, making them impractical in real applications. In this paper, we present a novel four-nodes-per-cycle parallel architecture of FSD, with a breadth-first processing that allows for short critical path. The implementation achieves a throughput of 213.3 Mbps at 400 MHz clock frequency, at a cost of 0.18 mm2 Silicon area on 0.13m CMOS technology. The proposed solution is much more economical compared with the existing FPGA implementations, and ver...
Bin Wu, Guido Masera
Added 25 Dec 2010
Updated 25 Dec 2010
Type Journal
Year 2010
Where CORR
Authors Bin Wu, Guido Masera
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