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2004
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Operation tables for scheduling in the presence of incomplete bypassing

9 years 2 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing has significant impact on cycle time, area, and power consumption of the processor. Due to the strict constraints on performance, cost and power consumption in embedded processors, architects need to evaluate and implement incomplete register bypassing mechanisms. However traditional data hazard detection and/or avoidance techniques used in retargetable schedulers break down in the presence of incomplete bypassing. In this paper, we present the concept of Operation Tables, which can be used to detect data hazards, even in the presence of incomplete bypassing. Furthermore our technique integrates the detection of both data, as well as resource hazards, and can be easily employed in a compiler to generate better schedules. Our experimental results on the popular Intel XScale embedded processor platform show that ...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt,
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where CODES
Authors Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau
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