Optical and Electrical Testing of Latchup in I/O Interface Circuits

Backside light emission and electrical measurements were used to evaluate the susceptibility to latchup of externally cabled I/O pins for a 0.13 µm technology generation [1,2] test chip, which was designed in a flip-chip package. Case studies of several Inputs/Outputs (I/Os) are shown along with conclusions regarding layout and floorplanning to ensure the robustness to various types of latchup trigger events.

• Type: Conference
• Year: 2003
• Where: ITC
• Authors: Franco Stellari, Peilin Song, Moyra K. McManus, Robert Gauthier, Alan J. Weger, Kiran V. Chatty, Mujahid Muhammad, Pia Sanda
• Keywords: Conclusions Regarding Layout, Hardware, ITC 2003, Latchup Trigger Events, µm Technology Generation